Reducing SoC Simulation and Development Time

T o remain competitive, system-on-chip (SoC) designers must keep pace with silicon technology’s rapid evolution. New communication, consumer, and computer product designs must exhibit rapid increases in functionality, reliability, and bandwidth—and rapid declines in cost and power consumption. All these improvements dictate increasing use of high-integration silicon, in which designers traditionally use register-transfer-level (RTL) hardware to realize data-intensive capabilities. Three forces— the design productivity gap, the growing cost of nanometer-level semiconductor manufacturing, and the global time-to-market imperative—put intense pressure on chip designers to develop more complex systems ever more quickly and cheaply. One approach to speeding development of megagate SoCs uses multiple microprocessor cores to perform much of the processing currently relegated to RTL techniques. Although general-purpose embedded processors can handle many tasks, they often lack the bandwidth needed to perform particularly complex jobs such as audio and video processing. Hence the historic rise of RTL use in SoC design. Developers can configure a new class of processor—automatically generated extensible microprocessor cores such as Tensilica’s Xtensa, or usermodifiable cores such as MIPS Technologies’ M4K—to bring the required amount and type of processing bandwidth to bear on many embedded tasks. Because these configurable processors employ firmware instead of RTL-defined hardware for their control algorithm, designers can develop and verify processor-based task engines for many embedded SoC tasks more quickly and easily than they could develop and verify RTL-based hardware blocks that perform the same tasks.